Impact of System and Cache Bandwidth on Stencil Computations Across Multiple Processor Generations

We compare old single-core multi-processor systems against multi-core processors and study the question which improvements are most relevant for increasing the performance on stencil computations. Even before the multi-core era began, the bandwidth wall, the discrepancy between off-chip bandwidth requirements and system bandwidth performance, was already a significant problem. Because of the currently growing number of parallel cores in CPUs this discrepancy could only be stopped from further deterioration by introducing dual-, tripleand quad-channel memory interfaces. However, this type of off-chip bandwidth scaling is too expensive and thus only a temporary relieve that cannot keep up indefinitely with the exponentially growing number of cores. Therefore, we analyze in particular how the scaling of system and cache bandwidth affects the performance of stencil computations. We evaluate both naive stencil implementations as well as time skewing variants that exploit temporal locality and minimize the number of cache misses in case of iterative stencil computations. We prove certain invariance properties of the schemes and develop a corresponding performance model. Then, we use this model to find out which hardware improvements in the old single-core processors are necessary to match the performance of the new multi-core processors. From this we can draw conclusions about most effective improvements for future processors.